In a conventional portable telephone, a baseband processor (hereinafter, “BP”) is in charge of a communication and call functions; and an application processor (hereinafter, “APL”) is in charge of the other multi-media processes. The BP further causes a digital signal processor (DSP) to execute a sound codec process of encoding and decoding the sound used by the call function (see, e.g.: “Zuno-Hodan (Brain Free Talk), No. 20, Will Hitachi change portable telephones using S-MAP? [online]”, [retrieved on Mar. 18, 2010], the Internet <http://www.atmarkit.co.jp/fpc/rensai/zunouhoudan020/smap.html>; @IT, “Zuno-Hodan, No. 44, Semiconductor of Japan—Is a portable telephone a trigger for its revitalization? [online]” [retrieved on Mar. 18, 2010], the Internet <http://www.atmarkit.co.jp/fsys/zunouhoudan/044zunou/app_processor.html>; and Mobile, “OMAP” of TI—Employed by NEC, Matsushita, and Fujitsu for 3G portable telephones [online]”, [retrieved on Mar. 18, 2010], the Internet <http://plusd.itmedia.co.jp/mobile/0203/18/n_omap.html>). The DSP is a processor that is developed aiming at executing a specific computing process at a high speed and that is used to mainly execute sound processing, image processing, etc. In this manner, the processor controlling the portable telephone is a heterogeneous multi-core processor system that includes processors executing processes each different from each other such as the BP, the APL, and the DSP.
A technique is disclosed as a technique of saving electrical power of a heterogeneous multi-core processor system, according to which the electrical power saving is facilitated by selecting a central processing unit (CPU) to which a program is assigned based on whether the processor is driven by an external power source or a battery from a dedicated CPU and a general-purpose CPU (see, e.g., Japanese Laid-Open Patent Publication No. 2008-276395).
Because the APL is in charge of the high-load multi-media processes, its computing capacity significantly varies depending on the multi-media process that the APL is executing. Therefore, the APL may include a clock gear function as a function of varying clock frequency. The clock gear function is a function that is able to cause the frequency to vary stepwise. The clock gear function included in the APL often is able to vary the frequency at three to five levels. In this manner, the APL is able to facilitate electrical power saving by varying a clock gear according to the multi-media process that the APL is executing.
However, among the conventional techniques, in the technique according to the above Japanese Laid-Open Patent Publication No. 2008-276395, the CPU to which the program is assigned is selected depending on whether the power source is an external power source or a battery. When a battery is used, a low-performance CPU is selected that presents an electrical power saving state and therefore, a problem arises in that the speed to execute a program is always low even when the battery has sufficient electrical power. Even when the electrical power is saved using the clock gear function, the number of levels set using the clock gear is small and therefore, a difference is generated for the multi-media process under execution between the proper computing capacity and the computing capacity of the APL. Therefore, a problem arises in that a surplus of the computing capacity is generated.